As the saying goes “Every thing has two sides”. So there is no exception in the FPGA market. Despite the promising market, FPGA has to face another four challenges, in addition to continuingly empowering IC with new technology and process.
First: improve performance and integration. For instance, despite significantly increased data traffic, smartphone is posing increasingly high requirements for bandwidth and speed; upgraded fixed-line communications require performance improvement for chip solution. At the same time, market is driving chip increasing integration to reduce system cost.
Second: lower power consumption. FPGA manufacturers would make great efforts to reduce power consumption and decrease system cost which can be seen through performance enhance and integration increase. However, power consumption decline should change chip architecture and process node; and process innovation is not easy.
Microsemi is superior in low power consumption, small size and leading reliability and security. These advantages come from cost-optimized non-volatile FPGA architecture.
“We beef up traditional strength with new advantages, and release products with more functions than other cost-optimized FPGA. We plan to use these architectures to win success of FPGA market; we know other makers are striving to up integration, even at the cost of component cost and power consumption rising. We believe there is better ways for balancing integration and power consumption/cost,” says Peera.
Third: reduce system cost. Peera noted as FPGA is rapidly becoming the core of data path, technologies enabling achieving chip integration on FPGA will boom. Single-level (integrating different functions on a single silicon core) and multilevel (using advanced packaging technology to integrate different chips into a single package) integration approach will see increasing adoption.
“Based on choices, system architects and developers will always favor programmability,” he says, “I think the trend enlarging leveraging
programmable logic devices will not fades, as long as it does not lead into uptick of BOM cost and power consumption.”
As the only China-based FPGA vendors standing among oversea giants, Dou Xiangfeng in Capital Microelectronics also praises providing customers with optimal programmable products. He believes some suppliers will develop their own products to meet different application direction; but this may fail to meet customers’ function demand.
Capital Microelectronics’ strategy is integrating more functions and offering better packaging than rivals. Meanwhile, it will capitalize on more advanced technology in high-end products, and continuously perfect functions, such as using SERDES technology in the same-capacity chip to make performance more advanced.
Wu also notes that his company will launch ARM-based medium-size FPGA, hard-core Cortex-M3 and rich peripherals and logic resources to offer customers comprehensive SoC products; the target application segments are motion control, and consumer electronics.
He explains “Hard-core M3 can provide customers with cost-effective solutions; if using soft-core processor, software engineers think designers needs time to understand FPGA architecture in the integration of FPGA and soft-core, which goes against product into market; and despite the high processing capability, A9 is not economical for clients. Our processors have been optimized, and see great innovation in efficiency and interface.”
Fourth,
ease to use and ecosystem. Since
FPGA manufacturers are committed to integration trends, it can be expected software tools will focus on making integration easier. This includes improving circuit layout of front-end design entry, as well as achieving more high-level design abstraction with advanced design ways.
“When integrating embedded processors, there is a dedicated module in FPGA for processor development; and the module will continue developing and improving to integrate hardware and firmware together. Finally, we estimate power consumption optimization will push on, including reporting power usage and allowing power designers to optimize design,” says Peera, “For ecosystem development, we expect in-tool encryption method to standard on the basis of IEEE rule, which enables the third party to easier offer open market IP macro-module and core.
Altera also stressed “Providing hardware designers, embedded software developers and programmers with high-quality, productivity-centric design tools, pre-verified IP cores and development boards is Altera's strategic emphasis. For hardware designers, Altera continues to improve compilation time; Quartus II software can offer industry’s highest compile times, offering higher-level abstraction for more efficient design entry. In addition, there are software programmers-faced OpenCL SDK and supporting-embedded designers high-end design process and embedded design kits. These features combine with software’s advanced synthesis engine, helping design teams efficiently and quickly complete their designs.”
Meanwhile, Altera places emphasis on the support of SoC partners, hoping to create a complete embedded ecosystem together. To date, there are lots of embedded operating system and development tools announcing supporting Altera SoC FPGA.
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SoC FPGA, challenges, FPGA market,