Foundry On the 21st, UMC announced the launch of its 40nm embedded Super Flash nonvolatile memory process platform with Silicon Storage Technology (SST). The new 40nm SST embedded flash memory reduces unit size by more than 20% from the current production of 55nm and shrinks the overall memory area by 20% to 30%. At present, the Japanese semiconductor maker Toshiba Electronic Components and Storage Products Company has begun to evaluate the applicability of its microprocessor (MCU) chip to the UMC 40nm SST technology process platform.
UMC said that at present there are more than 20 customers and products are UMC 55 nm SST process technology embedded flash memory process for all stages of production. Its products include SIM cards, financial transactions, automotive electronics, Internet of Things, MCUs, and other applications. For a new generation of 40-nanometer SST process technology embedded flash memory process platform, Toshiba Electronic Components and Storage Products Corporation mixed signal chip division vice president Matsui Jun pointed out that Toshiba looks forward to UMC's 40-nanometer SST process technology to enhance MCU products performance. In cooperation with UMC, it will be able to provide flexible production capacity through stable manufacturing and supply in line with Toshiba's production needs and will also be able to maintain its strong business continuity plan.
Ding Wenqi, Associate Director of UMC Special Technology Organization, said that since 2015, UMC has been receiving high attention from customers since UMC started to provide embedded flash memory with 55nm SST process technology as the mainstream technology. Because of this process platform with low power consumption, high reliability and superior data retention and high durability features can be used for automotive, industrial, consumer and Internet of Things applications. In the future, these embedded flash solutions will expand Toshiba into the 40nm process technology platform, bringing the high speed and reliability of SST process technology to Toshiba and other foundry customers.
UMC pointed out that the separate gate memory cell SST process is based on the standard set by JEDEC standards, with 100K durability, and 85 ℃ and the operating temperature range of -40 ℃ to 125 ℃ under the circumstances, the data can be saved 10 years of performance. At this stage in addition to the 40-nanometer SST process technology, there are more than 20 customers UMC's 55-nanometer SST process technology to produce various types of applications.
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