According to relevant reports, Samsung Electronics plans to build a V10 NAND production line from March 2026 and start formal mass production in October. This is also the first time that Samsung Electronics has clearly disclosed the mass production plan of V10 NAND. It was previously observed that Samsung would mass produce V10 this year, but Samsung finally set the commercialization time in 2026.
According to Samsung's plan, relevant equipment will be introduced in March 2026, and the production line will be completed within the first half of the year. After trial production and stability testing, mass production will be officially started in October. The relevant investment plan is expected to be officially launched in the second half of this year.
In order to increase storage capacity, the development route of NAND flash memory technology is mainly achieved by vertically stacking storage units. At present, Samsung's stacked product is 286-layer V9 NAND, which has been mass-produced since last year. V10 adds 100+ layers to V9, reportedly reaching 430 layers. According to the specifications previously revealed by Samsung Electronics, the storage density calculated by TLC standard reaches 28Gb/mm?, which is 56% higher than the previous generation; the input and output interface speed is 5.6GT/s, which is 75% higher. Such a significant performance leap makes it possible to work with the PCIe Gen6 master controller that will be commercially available next year to develop the data center market.
It is worth mentioning that V10 will apply a number of new technologies due to the increase in the number of stacked layers. First, it uses ultra-low temperature (below -70℃) etching equipment punching technology for the first time for data transmission channel processing between vertically stacked storage units. Samsung is currently evaluating the use of equipment from Lam Research and TEL. The characteristic of low-temperature etching equipment is that it can etch at very low temperatures and at very high speeds, which can reduce stacking problems during NAND etching. Secondly, unlike the previous generation of products manufactured on a single wafer, the V10 innovatively adopts "hybrid packaging" technology, that is, the "unit" storing data and the "periphery" of the driving circuit are made on different wafers and then bonded. This technology is called "wafer-to-wafer (W2W) bonding". In addition, Samsung also introduced molybdenum (Mo) elements for word line (the line connected to the source part of the transistor, responsible for reading and writing) materials to replace tungsten (W) and titanium nitride (TiN) materials, which can significantly reduce the "resistance" in the transistor.
Samsung is expected to adopt the performance-upgraded V10 products and focus on the development of eSSDs for data centers. However, the relevant person in charge of Samsung Electronics said about the V10 investment and mass production plan: "It is being promoted according to internal plans, but the specific details cannot be confirmed."
At the same time, SK Hynix is ??also working on NAND with more than 400 layers. According to previous reports, SK Hynix is ??also exploring the manufacture of 3D NAND products with more than 400 layers and plans to mass produce them in 2025. Instead of testing at its own fab, SK Hynix sent test wafers to Tokyo Electron (TEL) to test the performance of the latter's cryogenic etching equipment. Unlike existing equipment that usually operates at 0-30°C, TEL's new etching equipment is capable of high-speed etching at -70°C. Its memory channel hole etching technology can achieve high-aspect ratio etching of 10 microns deep in just 33 minutes, and can also reduce the global warming potential by 84% compared to previous technologies.
SK Hynix plans to use a three-layer stacking structure in 321-layer NAND. However, achieving uniformity is a major challenge when it comes to deep channel hole etching. Therefore, companies usually use a double-layer or even a triple-layer stacking structure for 3D NAND manufacturing due to the considerable difficulty of etching vertical holes. With TEL's new etching equipment, it may be possible to manufacture 3D NAND with more than 400 layers in the future, even for structures with fewer stacking layers, allowing memory manufacturers to reduce costs by simplifying the process. SK Hynix aims to produce 3D NAND products with more than 400 layers, and these NAND chips may adopt a single-layer or double-layer stacking structure depending on their performance.
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